Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - fpga ddr

Search list

[VHDL-FPGA-Verilog] Xilinx spartan 6 DDR 测试源代码

Description: Xilinx FPGA Spartan 6 上可运行的软核microblaze以及外设DDR, SPI,UART等测试代码
Platform: | Size: 18476664 | Author: jameszhou9019 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776192 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 677888 | Author: 钟方 | Hits:

[VHDL-FPGA-Verilog] ddr_cntl_a_withtb

Description: arm控制FPGA的DDR测试代码，共享一下-arm control FPGA DDR test code sharing what
Platform: | Size: 2384896 | Author: yourname | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: DDR sdram 包含的完整的源码,仿真的相关文件-DDR sdram contains complete source code, simulation of the relevant documents
Platform: | Size: 1021952 | Author: 飞翔 | Hits:

[VHDL-FPGA-Verilog] ddr

Description: ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）
Platform: | Size: 1022976 | Author: yuling | Hits:

[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114688 | Author: | Hits:

[VHDL-FPGA-Verilog] ddr_ctrl

Description: verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
Platform: | Size: 27648 | Author: 王郁 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: 基于FPGA 实现DDR SDRAM的控制器-FPGA-based realization of DDR SDRAM controller
Platform: | Size: 474112 | Author: 张宁 | Hits:

[VHDL-FPGA-Verilog] rtl

Description: DDR控制器 已通过FPGA 验证 大家不要错过哦-DDR controller has passed FPGA to verify that we will not miss Oh
Platform: | Size: 52224 | Author: kin | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: 利用fpga读写ddr的源代码 实测可以使用-Ddr use FPGA to read and write the source code can use the measured
Platform: | Size: 474112 | Author: 朱宝军 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA-DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
Platform: | Size: 676864 | Author: 黄达 | Hits:

[Software Engineering] DDR2_hardcore_userguide

Description: xillinx Spartan6 FPGA DDR 接口设计指南-xillinx Spartan6 FPGA DDR Interface Design Guidelines
Platform: | Size: 2324480 | Author: james | Hits:

[VHDL-FPGA-Verilog] ddr_sdr_V1_1

Description: DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device
Platform: | Size: 37888 | Author: jordanliang | Hits:

[VHDL-FPGA-Verilog] Twister_DDR_SDRAM_Board_Manual

Description: Twister DDR EP1C6Q240 FPGA 开发板 原理图，PCB,BOM-Twister Board Documentation Schematics, PCB and BOM Rev. B
Platform: | Size: 1452032 | Author: SEED | Hits:

[VHDL-FPGA-Verilog] ddr_code

Description: 基于FPGA的DDR SDRAM控制器的VHDL硬件描述语言-FPGA-based DDR SDRAM controller VHDL hardware description language
Platform: | Size: 11264 | Author: 阳阳 | Hits:

[VHDL-FPGA-Verilog] FPGA-DDR-SDRA

Description: 基于FPGA 的DDR SDRAM高速数据采集的应用-DDR SDRAM high-speed FPGA-based data acquisition applications
Platform: | Size: 309248 | Author: 周勇 | Hits:

[VHDL-FPGA-Verilog] ddr

Description: 基于FPGA的ddr控制器的设计与实现，verilog，ISE-FPGA-based controller design and implementation of ddr, verilog, ISE
Platform: | Size: 179200 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] FPGA-SDRAM-control-code

Description: 该程序是FPGA控制DDR SRAM的控制源代码，使得SDRAM的控制变得简单。-This program is DDR SDRAM control code ,it makes the operation of SDRAM more easy.
Platform: | Size: 41984 | Author: didi | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM_IP_core

Description: DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
Platform: | Size: 474112 | Author: zyy | Hits:
« 12 3 4 5 »

CodeBus www.codebus.net